[Rockefeller Center, New York City, Summer '09]

Rudrajit Datta

Intel Corporation

Ronler Acres
Hillsboro, OR 97124

Phone: +1 512 484-2834
Email: rudrajit at utexas dot edu (best way to contact me)

About Me

I have recently joined Intel as a CAD engineer at their Ronler Acres campus in scenic Hillsboro, OR. At Intel I work on identifying and analyzing issues affecting yield in latest technological nodes and coming up with CAD based solutions, with a focus on memory caches. Before joining Intel I received my PhD from the Department of Electrical and Computer Engineering at The University of Texas at Austin, where I worked in the Computer Aided Testing (CAT) Lab under Prof. Nur Touba. I finished Bachelor of Technology in Electrical Engineering from Indian Institue of Technology, Kharagpur in 2007.

I jabber at @rudrajitdatta, post photos on 500px, Flickr and an infrequently maintained blog, also randomly muse about delicious grub at thegourmetlens.


In my PhD thesis I looked at the effect of soft error rates (SER) on semiconductor memories and how these adverse affects can be mitigated by efficient usage of error correction codes (ECC). I proposed several solutions to enhance ECC used in present day micro-processors' memories via post-silicon characterization tests and also how error correction can be adapted for application to next generation memory elements.
In addition I have a broad interest in design for testability (DFT) and development of CAD tools to make life easier for those enagaged in the creative and often under-appreciated fields of debug and diagnosis.
My Resume [PDF]


[1] R. Datta, N. A. Touba, "Exploiting Unused Spare Columns to Improve Memory ECC", Proc. of IEEE VLSI Test Symposium, pp. 47-52, May 2009. [pdf] [ppt]

[2] R. Datta, N. A. Touba, "Post-Manufacturing ECC Customization Based on Orthogonal Latin Square Codes and Its Application to Ultra-Low Power Caches", Proc. of IEEE International Test Conference, November 2010. [pdf] [ppt]

[3] R. Datta, N. A. Touba, "Designing a Fast and Adaptive Error Correction Scheme for Increasing the Lifetime of Phase Change Memories", Proc. of IEEE VLSI Test Symposium 2011, pp. 134-139, May 2011. [pdf] [ppt]

[4] R. Datta, N. A. Touba, "X-Stacking A Method for Reducing Control Data for Output Compaction", Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 332-338, October 2011. [pdf]

[5] R. Datta, N. A. Touba, "Generating Burst-error Correcting Codes from Orthogonal Latin Square Codes a Graph Theoretic Approach", Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 367-373, October 2011. [pdf] (Received Best Student Paper Award)

[6] J.-S. Yang, R. Datta, "Efficient Function Mapping in Nanoscale Crossbar Architecture", Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 190-196, October 2011. [pdf]

[7] R. Datta, "Adaptable and Enhanced Error Correction Codes for Efficient Error and Defect Tolerance in Memories", Ph.D. Dissertation, The University of Texas at Austin, December 2011. [pdf]


[1] R. Datta, N.A. Touba, "Improving Memory Reliability via Post-Silicon Methods", Advanced Micro Devices, Austin, TX, August 2010.

[2] R. Datta, N. A. Touba, "Improving Memory ECC by Exploiting Unused Spare Columns", International Test Synthesis Workshop, March 2009. (Received Best Student Presentation Award)

Work Experience

  • Intel Corporation

  •    - Software Engineer, Debug and Diagnosis Solutions Group, Hillsboro, January '12 - Present.
       - Graduate Intern, Debug and Diagnosis Solutions Group, Hillsboro, May '11 - August '11.
       - Graduate Intern, System Validation Full Chip - Power Management/DFx, Atom Validation & Emulation Group (AVE), Austin, June '09 - August '10.
       - Graduate Intern, DFx Architecture, SOC Enabling Group (SEG), Hillsboro, June '08 - August '08.

  • Goldman Sachs

  •    - Summer Analyst, Proprietory Accounting and Risk Analysis (PARA), Bangalore, May '06 - July '06.


    HSpice: This is a comprehensive manual for HSpice commands. Some more HSpice documentation can be found here.
    PrimeTime: PrimeTime is a static timing analyzer (STA) tool by Synopsys. Here's a useful help documentation (not authored by me).
    Algorithms: The video lectures from the algorithms class of MIT proved quite helpful to me.
    Similar classes at Berkeley, Stanford, UIUC, Cornell.
    Java: The best place to go when one needs any Java-related help is the Sun Java tutorials.
    C/C++: A useful reference for C/C++ functions is this Wiki. It doesn't include aome of the advanced functions but nevertheless a handy reference to have.
    Perl: This is one scripting language I use extensively. And the Perl Monks have bailed me out many a times when I needed help with Perl. Another tutorial which is also quite resourceful.
    VLSI: EE Times and DeepChip.com are two great resources for the latest trends in VLSI design and CAD. AnandTech.com is another good website if you're interested in the technical details of common electronic devices.

    Colleagues & Friends

    Joon Sung Yang - http://users.ece.utexas.edu/~jsyang
    Shreepriya Das - http://users.ece.utexas.edu/~sdas1
    Sushovan De - http://sushovande.6te.net
    Mahesh Prabhu - http://www.cerc.utexas.edu/~mprabhu/

    Last updated: January 27th, 2013